1. Field of the Invention
This invention relates to nonvolatile semiconductor memory devices made up of nonvolatile transistors and allowing the stored data to be replaced by other data.
2. Description of the Related Art
This type of nonvolatile semiconductor memory device is well known as an EPROM (erasable and programmable read only memory). One of the known memory cells, which are used for the EPROM, is a double layered type transistor. In this transistor, floating and control gate electrodes are layered in the channel region, which is located between the source and drain regions.
The prior memory cell based on the double gate type transistor is illustrated in cross-sectional form in FIG. 1. As shown, source region S and drain region D, as N type diffusion layers, are separately formed in the surface region of P type semiconductor substrate 50. Channel region 51 is located between source and drain regions S and D. A first gate insulating film (not shown) is formed on channel region 51. Floating gate electrode 52 made of polycrystalline silicon, for example, is further formed on the first gate insulating film. A second gate insulating film (not shown) is formed on floating gate electrode 52. Control gate electrode 53, which is made of polycrystalline silicon, is laid on the second gate insulating film.
The memory cell thus structured can be electrically depicted as an equivalent circuit, as shown in FIG. 2. A bit line BL is connected to the drain region D of transistor 60 used as a memory cell. The control gate electrode 53 is connected to control gate line CG. The source region S is connected to ground GND.
The memory cell thus arranged operates in three modes, write, erase, and read modes. These operation modes, and voltages at the source region S, bit line BL and control gate line CG, are tabulated as in FIG. 3. The integrated circuit containing the EPROM uses three power voltages, GND, Vcc and Vpp; GND=0V (ground), Vcc=5V, and Vpp=12.5V.
The write mode will first be described. This mode is called an electron injection mode. In this mode, electrons are injected into floating gate electrode 52 to raise the threshold voltage of cell transistor 60. The voltages at the respective portions in this mode are: BL=12.5, CG=12.5, and S=0V. In operation, an intensive electric field is concentrated in the depletion layer, which is formed particularly in the vicinity of the drain region D. Electrons travel from the source region S of transistor 60 toward drain region D. The electrons toward the drain region D are accelerated by the electric field concentrated near the drain region D, and gain enough energy to jump over the energy barrier of the first gate insulating film (not shown), from the surface of substrate 50. This type of electrons are called hot electrons. The hot electrons are attracted by the high voltage applied to the control gate electrode 53, and pass through the first gate insulating film, and enter into floating gate electrode 52, and are arrested there. As a result, the floating gate 52 is negatively charged, and in the region of the substrate under floating gate electrode 52, i.e., in the channel region 51, it is difficult for the inversion of conductivity or channel formation to occur. In other words, the threshold voltage of cell transistor 60 substantially rises.
The data erase mode is also called an electron emission mode. In this mode, the memory cells are radiated with ultraviolet rays. The radiated ultraviolet rays excite the electrons, which are injected into floating gate electrode 52 in the data write mode. The excited electrons jump over the energy barrier of the second insulating film (not shown) and enter into control gate electrode 53. The electrons also jump over the energy barrier of the first insulating film (not shown) to enter into substrate 50. Such flow of electrons reduces the threshold value of cell transistor 60.
In the data read mode, the respective voltages are: BL=2V, CG=5V, and S=0V. In this mode, when the electrons have been injected into floating gate 52, the threshold voltage of the cell transistor is large. Under this condition, no channel is formed between the source and drain regions, thereby prohibiting the flow of cell current. The bit line voltage is kept at 2V. When the electrons are being emitted from the electrode, the threshold voltage of cell transistor 60 is small. Therefore, a channel is formed between the source and drain regions, to allow the cell current to flow. Further, the bit line voltage drops to approximately 0V. In this way, when the data is read out, the bit line voltage change in accordance with whether or not electrons are injected into or emitted from floating gate electrode 52. The voltage change on the bit line is amplified by a sense amplifier (not shown). This provides logical "1" or "0" of the data as read out from cell transistor 60.
It is in the data read out mode that a memory cell problem arises in the prior art memory device. This is caused by the fact that the small 2V voltage is amplified by the sense amplifier. The sense amplifier must amplify this small voltage to such a level as to enable discrimination of logical "1" or "0". Therefore, the sense amplifier must have a high performance characteristic. This fact implies that the circuit design is difficult, the circuit is complicated, and the cost to manufacture is high.
The reason why the bit line voltage BL must be held at about 2V, and not a larger voltage such as 5V, in the read mode, will be described. When BL=5V, the voltage of drain region D is 5V. Under this condition, the electric field is concentrated in the vicinity of drain region D as in the data write mode, and is weaker in intensity than that of the electric field in the write mode. When the cell transistor in which no electrons are emitted, is subjected to the read mode for a long time, electrons are injected little by little into floating gate electrode 52, so that the threshold voltage of the cell transistor gradually rises. After a predetermined period of time elapses, enough electrons have been injected into floating gate electrode 52 to invert the logical level of the data stored in the cell transistor. As a result, erroneous data will be read out from the cell transistor. Such a phenomenon is called a soft write (weak write). The characteristic of the soft write phenomenon with respect to the time lapse is called a read retention characteristic (data hold characteristic).
The read retention characteristic is enhanced, by constraining the soft write phenomenon. A possible way to improve the read retention characteristic is to decrease the bit line voltage in the read mode. In this approach, however, a difference between the bit line potentials when the electrons are being injected into the cell transistor and when they are emitted from the transistor, is small, and narrows the logical margin in the read mode. It is for this reason that decreasing the bit line potential in the read mode is limited to about 2V, BL=2V. With BL=2V, the read retention characteristic can be improved. To accommodate the small logical margin problem, high performance sense amplifiers are used for sensing the bit line potential difference.
Thus, conventionally the solution of this problem depends only on the sense amplifier. This causes many problems. A first problem is the complicated circuit of the sense amplifier. To fabricate such a complicated circuit into semiconductor chip, a large chip area is required, resulting in increase of cost to manufacture. A second problem is the reduced margin for the power voltage in the read mode. This is problematic particularly for the low voltage operation. A third problem is the need for the constant voltage source of 2V to be supplied to the bit line. The prior memory device must contain a circuit for forming such an intermediate voltage, resulting in increase of power consumption.
As described above, the prior nonvolatile memory device involves many problems; the increased chip area, unstable low voltage operation, and increased power consumption.